Typically, a memory device will be coupled to an external control device such as a microprocessor. The microprocessor may be incorporated into a personal computer, a personal digital assistant, a telephone, a camera, or other device requiring a nonvolatile memory. A multitude of devices including PDAs, wireless devices, and cell phones continue to evolve and incorporate new multifunction capabilities. New capabilities include Web access, a digital camera, video, and music storage. To be marketable, these new devices must provide new capabilities at lower costs and in smaller spaces. In addition, nonvolatile memory devices must have higher capacities, improved speed, and improved interface flexibility.
For example, in the cell phone market, previous voice only cell phones utilized approximately 4 to 8 megabytes of memory to store data such as phone numbers, call logs, or messages. Currently, consumers now demand cell phones that are feature-rich. New cell phone devices now include Internet browsing, text messaging, games, Java applications, music, and digital cameras. These exemplary applications have caused an increase in memory requirements. Typically, cell phone manufacturers now use 64 to 256 megabytes or more memory to store large amounts of data including pictures and music.
Memory options when designing cell phones are numerous; a conventional memory architecture for a multifunction cell phone may use NOR flash for code storage, PSRAM for workspace, and NAND flash for data storage. Some designers also include SRAM for backup. NAND flash memory currently has the lowest cost per bit, however, NAND flash memory also has a slower random access time compared to other memory types and no capability for byte level programming.
A read access cycle time for NAND flash memory may be approximately 25 milliseconds. However, in typical applications, stored data is read into a page register and the data may be serially clocked from the memory device within a 50 nanosecond clock cycle. For example, U.S. Pat. No. 5,488,711 to Hewitt et al. describes a write cache for reducing the time required to load data into an EEPROM device. Although the architecture described by Hewitt et al. improves the performance of the memory device, further performance increases using different or improved architectures are possible.